Inter-Processor Communications (IPC)

The IPC allows communication between the two CPU subsystems (i.e. CPU1 and CPU2).

• Message RAMs
• IPC flags and interrupts
• IPC command registers
• Flash pump semaphore
• Clock configuration semaphore
• Free-running counter

All IPC features are independent of each other

IPC Global Shared RAM

There are up to 16 blocks of shared RAM on F2837xD devices. These shared RAM blocks are typically used by the application, but can also be used for transferring messages and data. Each block can individually be owned by either CPU1 or CPU2.

CPU1 core ownership:
At reset, CPU1 owns all of the shared RAM blocks. In this configuration CPU1 core can freely use the memory blocks. CPU1 can read, write or execute from the block and CPU1.DMA can read or write. On the CPU2 core, CPU2 and CPU2.DMA can only read from these blocks. Blocks owned by the CPU1 core can be used by the CPU1 to send CPU2 messages. This is referred to as C1toC2.

CPU2 core ownership:
After reset, the CPU1 application can assign ownership of blocks to the CPU2 subsystem. In this configuration, CPU2 core can freely use the blocks. CPU2 can read, write or execute from the block and the CPU2.DMA can read or write. CPU1 core, however can only read from the block. Blocks owned by CPU2 core can be used can be used to send messages from the CPU2 to CPU1. This is referred to as C2toC1.

IPC Message RAM

The F2837xD has two dedicated message RAM blocks. Each block is 1K words in length. Unlike the shared RAM blocks, these blocks provide communication in one direction only and cannot be reconfigured.

CPU1 to CPU2 C1toC2 message RAM:
The first message RAM is the CPU1 to CPU2 or C1toC2. This block can be read or written to by the CPU1 and read by the CPU2. CPU1 can write a message to this block and then the CPU2 can read it.

CPU2 to CPU1 C2toC1 message RAM:
The second message RAM is the CPU2 to CPU1 or C2toC1. This block can be read or written to by CPU2 and read by CPU1. This means CPU2 can write a message to this block and then CPU1 can read it. After the sending CPU writes a message it can inform the receiver CPU that it is available through an interrupt or flag.

IPC Message Registers

IPC Interrupts and Flags

When the sending CPU wants to inform the receiver that a message is ready, it can make use of an interrupt or flag. There are identical IPC interrupt and flag resources on both CPU1 core and CPU2 core.

4 Interrupts:
There are 4 interrupts that CPU1 can send to CPU2 (and vice-versa) through the Peripheral Interrupt Expansion (PIE) module. Each of the interrupts has a dedicated vector within the PIE, IPC0 – IPC3.

28 Flags:
In addition, there are 28 flags available to each of the CPU cores. These flags can be used for messages that are not time critical or they can be used to send status back to originating processor. The flags and interrupts can be used however the application sees fit and are not tied to particular operation in hardware.

Registers: Set, Flag, Clear, Status and Acknowledge
The registers to control the IPC interrupts and flags are 32-bits:

• Bits [3:0] = interrupt & flag
• Bits [31:4] = flag only

IPC Data Transfer

The F2837xD IPC is very easy to use. At the most basic level, the application does not need any separate software drivers to communicate between processors. It can utilize the message RAM’s and shared RAM blocks to pass data between processors at a fixed address known to both processors. Then the sending processor can use the IPC flag registers merely to flag to the receiving processor that the data is ready. Once the receiving processor has grabbed the data, it will then acknowledge the corresponding IPC flag to indicate that it is ready for more messages.

As an example:

1. CPU1 would write a message to the CPU2 in C1toC2 MSG RAM.
2. The CPU1 would write a 1 to the appropriate flag bit in the C1TOC2IPCSET register. This sets the C1TOC2IPCFLG, which also sets the C1TOC2IPCSTS register on CPU2, letting CPU2 know that a message is available.
3. CPU2 sees that a bit in the C1TOC2IPCSTS register is set.
4. CPU2 reads the message from the C1toC2 MSG RAM and then
5. It writes a 1 to the same bit in the C1TOC2IPCACK register to acknowledge that it has received the message. This subsequently clears the flag bit in C1TOC2IPCFLG and C1TOC2IPCSTS.
6. CPU1 can then send more messages using that particular flag bit.

IPC Software Solutions Summary

There are three options to use the IPC on the device.

Basic option: A very simple option that does not require any drivers. This option only requires IPC registers to implement very simple flagging of messages passed between processors.

Driver options: If the application code needs a set of basic IPC driver functions for reading or writing data, setting/clearing bits, and function calls, then there are 2 IPC software driver solutions provided by TI.

IPC-Lite:

• Only uses the IPC registers. No additional memory such as message RAM or shared RAM is needed.
• Only one IPC ISR can be used at a time.
• Can only process one message at a time.
• CPU1 can use IPC lite to communicate with the CPU2 boot ROM. The CPU2 boot ROM processes basic IPC read, write, bit manipulation, function call, and branch commands.

Main IPC Software API Driver:

• Utilizes circular buffers in C2toC1 and C1toC2 message RAM’s.
• Allows application to queue up to 4 messages prior to processing (configurable).
• Allows application to use multiple IPC ISR’s at a time.
• Requires additional setup in application code prior to use.

Reference

[1] TMS320F2837xD Microcontroller Workshop

Multichannel Buffered Serial Port (McBSP)

The McBSP provides a high-speed direct interface to codecs, analog interface chips (AICs), and other serially connected A/D and D/A devices. It has double-buffered transmission and triple-buffered reception for supporting continuous data streams. There are 128 channels for transmission and reception, and data size selections of 8, 12, 16, 20, 24, and 32 bits, along with µ-law and A-law companding.

Definition: Bit, Word, and Frame

Multi-Channel Selection

McBSP Summary

• Independent clocking and framing for transmit and receive
• Internal or external clock and frame sync
• Data size of 8, 12, 16, 20, 24, or 32 bits
• TDM mode – up to 128 channels
  • Used for T1/E1 interfacing
• µ-law and A-law companding
• SPI mode
• Direct Interface to many codecs
• Can be serviced by the DMA

Reference

[1] TMS320F2837xD Microcontroller Workshop

Universal Serial Bus (USB) Controller

The USB operates as a full-speed function controller during point-to-point communications with a USB host. It complies with the USB 2.0 standard, and a dynamically sizeable FIFO supports queuing of multiple packets.

USB Communication

Enumeration

USB Hardware

CAN Summary

• Complies with USB 2.0 specifications
• Full-speed (12 Mbps) Device controller
• Full- /Low-speed (12 Mbps/1.5 Mbps) Host controller
• The DMA controller may be used to read and write the USB FIFOs via software triggering
• Full software library with application examples is provided within C2000Ware

Reference

[1] TMS320F2837xD Microcontroller Workshop

Controller Area Network (CAN)

The CAN module is a serial communications protocol that efficiently supports distributed real-time control with a high level of security. It supports bit-rates up to 1 Mbit/s and is compliant with the CAN 2.0B protocol specification.

CAN does not use physical addresses to address stations. Each message is sent with an identifier that is recognized by the different nodes. The identifier has two functions – it is used for message filtering and for message priority. The identifier determines if a transmitted message will be received by CAN modules and determines the priority of the message when two or more nodes want to transmit at the same time.

CAN Bus and Node

The MCU communicates to the CAN Bus using a transceiver. The CAN bus is a twisted pair wire and the transmission rate depends on the bus length. If the bus is less than 40 meters the transmission rate is capable up to 1 Mbit/second.

Principles of Operation

• Data messages transmitted are identifier based, not address based
• Content of message is labeled by an identifier that is unique throughout the network
  • (e.g. rpm, temperature, position, pressure, etc.)
• All nodes on network receive the message and each performs an acceptance test on the identifier
• If message is relevant, it is processed (received); otherwise it is ignored
• Unique identifier also determines the priority of the message
  • (lower the numerical value of the identifier, the higher the priority)
• When two or more nodes attempt to transmit at the same time, a non-destructive arbitration technique guarantees messages are sent in order of priority and no messages are lost

Message Format and Block Diagram

The MCU CAN module is a full CAN Controller. It contains a message handler for transmission and reception management, and frame storage. The specification is CAN 2.0B Active – that is, the module can send and accept standard (11-bit identifier) and extended frames (29-bit identifier).

The CAN controller module contains 32 mailboxes for objects of 0 to 8-byte data lengths:

• configurable transmit/receive mailboxes
• configurable with standard or extended indentifier

The CAN module mailboxes are divided into several parts:

• MID – contains the identifier of the mailbox
• MCF (Message Control Field) – contains the length of the message (to transmit or receive) and the RTR bit (Remote Transmission Request – used to send remote frames)
• MDL and MDH – contains the data

The CAN module contains registers which are divided into five groups:

• Control & Status Registers
• Local Acceptance Masks
• Message Object Time Stamps
• Message Object Timeout
• Mailboxes

CAN Summary

• Fully compliant with CAN standard v2.0B
• Supports data rates up to 1 Mbps
• Thirty-two message objects
  • Configurable as receive or transmit
  • Configurable with standard or extended identifier
  • Programmable receive mask
  • Uses 32-bit time stamp on messages
  • Programmable interrupt scheme (two levels)
  • Programmable alarm time-out
• Programmable wake-up on bus activity
• Two interrupt lines
• Self-test mode

Reference

[1] TMS320F2837xD Microcontroller Workshop

Inter-Integrated Circuit (I2C)

The I2C provides an interface between devices that are compliant I2C-bus specification version 2.1 and connect using an I2C-bus. External components attached to the 2-wire serial bus can transmit or receive 1 to 8-bit data to or from the device through the I2C module.

I2C Operating Modes and Data Formats

I2C Summary

• Compliance with Philips I2C-bus specification (version 2.1)
• 7-bit and 10-bit addressing modes
• Configurable 1 to 8 bit data words
• Data transfer rate from 10 kbps up to 400 kbps
• Transmit FIFO and receive FIFO

Reference

[1] TMS320F2837xD Microcontroller Workshop

Serial Peripheral Interface (SPI)

The SPI is a high-speed synchronous serial port that shifts a programmable length serial bit stream into and out of the device at a programmable bit-transfer rate. It is typically used for communications between processors and external peripherals, and it has a 16-level deep receive and transmit FIFO for reducing servicing overhead. During data transfers, one SPI device must be configured as the transfer MASTER, and all other devices configured as SLAVES. The master drives the transfer clock signal for all SLAVES on the bus. SPI communications can be implemented in any of three different modes:

• MASTER sends data, SLAVES send dummy data
• MASTER sends data, one SLAVE sends data
• MASTER sends dummy data, one SLAVE sends data

In its simplest form, the SPI can be thought of as a programmable shift register. Data is shifted in and out of the SPI through the SPIDAT register. Data to be transmitted is written directly to the SPIDAT register, and received data is latched into the SPIBUF register for reading by the CPU. This allows for double-buffered receive operation, in that the CPU need not read the current received data from SPIBUF before a new receive operation can be started. However, the CPU must read SPIBUF before the new operation is complete of a receiver overrun error will occur. In addition, double-buffered transmit is not supported: the current transmission must be complete before the next data character is written to SPIDAT or the current transmission will be corrupted.

The Master can initiate a data transfer at any time because it controls the SPICLK signal. The software, however, determines how the Master detects when the Slave is ready to broadcast.

SPI Transmit / Receive Sequence

1. Slave writes data to be sent to its shift register (SPIDAT).
2. Master writes data to be sent to its shift register (SPIDAT or SPITXBUF).
3. Completing Step 2 automatically starts the SPICLK signal of the Master.
4. The MSB of the Master’s shift register (SPIDAT) is shifted out, and the LSB of the Slave’s shift register (SPIDAT) is loaded.
5. Step 4 is repeated until the specified number of bits are transmitted.
6. The SPIDAT register is copied to the SPIRXBUF register.
7. The SPI INT Flag bit is set to 1.
8. An interrupt is asserted if the SPI INT ENA bit is set to 1.
9. If data is in SPITXBUF, either Slave or Master, it is loaded into SPIDAT and transmission starts again as soon as the Master’s SPIDAT is loaded.

Since data is shifted out of the SPIDAT register MSB first, transmission characters of less than 16 bits must be left-justified by the CPU software prior to be written to SPIDAT.

Received data is shifted into SPIDAT from the left, MSB first. However, the entire sixteen bits of SPIDAT is copied into SPIBUF after the character transmission is complete such that received characters of less than 16 bits will be right-justified in SPIBUF. The non-utilized higher significance bits must be masked-off by the CPU software when it interprets the character. For example, a 9 bit character transmission would require masking-off the 7 MSB’s.

SPI Summary

• Synchronous serial communications
  • Two wire transmit or receive (half duplex)
  • Three wire transmit and receive (full duplex)
• Software configurable as master or slave
  • C28x provides clock signal in master mode
• Data length programmable from 1-16 bits
• 125 different programmable baud rates

Reference

[1] TMS320F2837xD Microcontroller Workshop

Serial Communications Interface (SCI)

The SCI is a two-wire asynchronous serial port (also known as a UART) that supports communications between the processor and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. A receiver and transmitter 16-level deep FIFO is used to reduce servicing overhead. The SCI transmit and receive registers are both double-buffered to prevent data collisions and allow for efficient CPU usage. In addition, the C28x SCI is a full duplex interface which provides for simultaneous data transmit and receive. Parity checking and data formatting is also designed to be done by the port hardware, further reducing software overhead.

The basic unit of data is called a character and is 1 to 8 bits in length. Each character of data is formatted with a start bit, 1 or 2 stop bits, an optional parity bit, and an optional address/data bit. A character of data along with its formatting bits is called a frame. Frames are organized into groups called blocks. If more than two serial ports exist on the SCI bus, a block of data will usually begin with an address frame which specifies the destination port of the data as determined by the user’s protocol.

The start bit is a low bit at the beginning of each frame which marks the beginning of a frame. The SCI uses a NRZ (Non-Return-to-Zero) format which means that in an inactive state the SCIRX and SCITX lines will be held high. Peripherals are expected to pull the SCIRX and SCITX lines to a high level when they are not receiving or transmitting on their respective lines.

When configuring the SCICCR, the SCI port should first be held in an inactive state. This is done using the SW RESET bit of the SCI Control Register 1 (SCICTL1.5). Writing a 0 to this bit initializes and holds the SCI state machines and operating flags at their reset condition. The SCICCR can then be configured. Afterwards, re-enable the SCI port by writing a 1 to the SW RESET bit. At system reset, the SW RESET bit equals 0.

Multiprocessor Wake-Up Modes

• Allows numerous processors to be hooked up to the bus, but transmission occurs between only two of them
• Idle-line or Address-bit modes
• Sequence of Operation
  • Potential receivers set SLEEP = 1, which disables RXINT except when an address frame is received
  • All transmissions begin with an address frame
  • Incoming address frame temporarily wakes up all SCIs on bus
  • CPUs compare incoming SCI address to their SCI address
  • Process following data frames only if address matches

The SCI interrupt logic generates interrupt flags when it receives or transmits a complete character as determined by the SCI character length. This provides a convenient and efficient way of timing and controlling the operation of the SCI transmitter and receiver. The interrupt flag for the transmitter is TXRDY (SCICTL2.7), and for the receiver RXRDY (SCIRXST.6). TXRDY is set when a character is transferred to TXSHF and SCITXBUF is ready to receive the next character. In addition, when both the SCIBUF and TXSHF registers are empty, the TX EMPTY flag (SCICTL2.6) is set. When a new character has been received and shifted into SCIRXBUF, the RXRDY flag is set. In addition, the BRKDT flag is set if a break condition occurs. A break condition is where the SCIRXD line remains continuously low for at least ten bits, beginning after a missing stop bit. Each of the above flags can be polled by the CPU to control SCI operations, or interrupts associated with the flags can be enabled by setting the RX/BK INT ENA (SCICTL2.1) and/or the TX INT ENA (SCICTL2.0) bits active high.

Additional flag and interrupt capability exists for other receiver errors. The RX ERROR flag is the logical OR of the break detect (BRKDT), framing error (FE), receiver overrun (OE), and parity error (PE) bits. RX ERROR high indicates that at least one of these four errors has occurred during transmission. This will also send an interrupt request to the CPU if the RX ERR INT ENA (SCICTL1.6) bit is set.

SCI Summary

• Asynchronous communications format
• 65,000+ different programmable baud rates
• Two wake-up multiprocessor modes
  • Idle-line wake-up & Address-bit wake-up
• Programmable data word format
  • 1 to 8 bit data word length
  • 1 or 2 stop bits
  • even/odd/no parity
• Error Detection Flags
  • Parity error; Framing error; Overrun error; Break detection
• Transmit FIFO and receive FIFO
• Individual interrupts for transmit and receive

Reference

[1] TMS320F2837xD Microcontroller Workshop

Quadrature Encoder Pulse Module (eQEP)

Reference

[1] TMS320F2837xD Microcontroller Workshop

Capture Module (eCAP)

Reference

[1] TMS320F2837xD Microcontroller Workshop

ePWM Module Signals and Connections

ePWM Block Diagram

ePWM Time-Base Sub-Module

ePWM Compare Sub-Module

ePWM Action Qualifier Sub-Module

ePWM Dead-Band Sub-Module

ePWM Chopper Sub-Module Purpose of the PWM Chopper

• Allows a high frequency carrier signal to modulate the PWM waveform generated by the Action Qualifier and Dead-Band modules
• Used with pulse transformer-based gate drivers to control power switching elements

ePWM Trip-Zone and Digital Compare Sub-Module

Purpose of the Digital Compare Sub-Module

• Generates compare events that can:
  • Trip the ePWM
  • Generate a Trip interrupt
  • Sync the ePWM
  • Generate an ADC start of conversion
• Digital compare module inputs are:
  • Input X-Bar
  • ePWM X-Bar
  • Trip-zone input pins
• A compare event is generated when one or more of its selected inputs are either high or low
• Optional Blanking can be used to temporarily disable the compare action in alignment with PWM switching to eliminate noise effects

ePWM Event-Trigger Sub-Module

Hi-Resolution PWM (HRPWM)

Reference

[1] TMS320F2837xD Microcontroller Workshop