Serial Communications Interface (SCI)

The SCI is a two-wire asynchronous serial port (also known as a UART) that supports communications between the processor and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. A receiver and transmitter 16-level deep FIFO is used to reduce servicing overhead. The SCI transmit and receive registers are both double-buffered to prevent data collisions and allow for efficient CPU usage. In addition, the C28x SCI is a full duplex interface which provides for simultaneous data transmit and receive. Parity checking and data formatting is also designed to be done by the port hardware, further reducing software overhead.

The basic unit of data is called a character and is 1 to 8 bits in length. Each character of data is formatted with a start bit, 1 or 2 stop bits, an optional parity bit, and an optional address/data bit. A character of data along with its formatting bits is called a frame. Frames are organized into groups called blocks. If more than two serial ports exist on the SCI bus, a block of data will usually begin with an address frame which specifies the destination port of the data as determined by the user’s protocol.

The start bit is a low bit at the beginning of each frame which marks the beginning of a frame. The SCI uses a NRZ (Non-Return-to-Zero) format which means that in an inactive state the SCIRX and SCITX lines will be held high. Peripherals are expected to pull the SCIRX and SCITX lines to a high level when they are not receiving or transmitting on their respective lines.

When configuring the SCICCR, the SCI port should first be held in an inactive state. This is done using the SW RESET bit of the SCI Control Register 1 (SCICTL1.5). Writing a 0 to this bit initializes and holds the SCI state machines and operating flags at their reset condition. The SCICCR can then be configured. Afterwards, re-enable the SCI port by writing a 1 to the SW RESET bit. At system reset, the SW RESET bit equals 0.

Multiprocessor Wake-Up Modes

• Allows numerous processors to be hooked up to the bus, but transmission occurs between only two of them
• Idle-line or Address-bit modes
• Sequence of Operation
  • Potential receivers set SLEEP = 1, which disables RXINT except when an address frame is received
  • All transmissions begin with an address frame
  • Incoming address frame temporarily wakes up all SCIs on bus
  • CPUs compare incoming SCI address to their SCI address
  • Process following data frames only if address matches

The SCI interrupt logic generates interrupt flags when it receives or transmits a complete character as determined by the SCI character length. This provides a convenient and efficient way of timing and controlling the operation of the SCI transmitter and receiver. The interrupt flag for the transmitter is TXRDY (SCICTL2.7), and for the receiver RXRDY (SCIRXST.6). TXRDY is set when a character is transferred to TXSHF and SCITXBUF is ready to receive the next character. In addition, when both the SCIBUF and TXSHF registers are empty, the TX EMPTY flag (SCICTL2.6) is set. When a new character has been received and shifted into SCIRXBUF, the RXRDY flag is set. In addition, the BRKDT flag is set if a break condition occurs. A break condition is where the SCIRXD line remains continuously low for at least ten bits, beginning after a missing stop bit. Each of the above flags can be polled by the CPU to control SCI operations, or interrupts associated with the flags can be enabled by setting the RX/BK INT ENA (SCICTL2.1) and/or the TX INT ENA (SCICTL2.0) bits active high.

Additional flag and interrupt capability exists for other receiver errors. The RX ERROR flag is the logical OR of the break detect (BRKDT), framing error (FE), receiver overrun (OE), and parity error (PE) bits. RX ERROR high indicates that at least one of these four errors has occurred during transmission. This will also send an interrupt request to the CPU if the RX ERR INT ENA (SCICTL1.6) bit is set.

SCI Summary

• Asynchronous communications format
• 65,000+ different programmable baud rates
• Two wake-up multiprocessor modes
  • Idle-line wake-up & Address-bit wake-up
• Programmable data word format
  • 1 to 8 bit data word length
  • 1 or 2 stop bits
  • even/odd/no parity
• Error Detection Flags
  • Parity error; Framing error; Overrun error; Break detection
• Transmit FIFO and receive FIFO
• Individual interrupts for transmit and receive

Reference

[1] TMS320F2837xD Microcontroller Workshop

Capture Module (eCAP)

Reference

[1] TMS320F2837xD Microcontroller Workshop

ePWM Module Signals and Connections

ePWM Block Diagram

ePWM Time-Base Sub-Module

ePWM Compare Sub-Module

ePWM Action Qualifier Sub-Module

ePWM Dead-Band Sub-Module

ePWM Chopper Sub-Module Purpose of the PWM Chopper

• Allows a high frequency carrier signal to modulate the PWM waveform generated by the Action Qualifier and Dead-Band modules
• Used with pulse transformer-based gate drivers to control power switching elements

ePWM Trip-Zone and Digital Compare Sub-Module

Purpose of the Digital Compare Sub-Module

• Generates compare events that can:
  • Trip the ePWM
  • Generate a Trip interrupt
  • Sync the ePWM
  • Generate an ADC start of conversion
• Digital compare module inputs are:
  • Input X-Bar
  • ePWM X-Bar
  • Trip-zone input pins
• A compare event is generated when one or more of its selected inputs are either high or low
• Optional Blanking can be used to temporarily disable the compare action in alignment with PWM switching to eliminate noise effects

ePWM Event-Trigger Sub-Module

Hi-Resolution PWM (HRPWM)

Reference

[1] TMS320F2837xD Microcontroller Workshop

Sigma Delta Filter Module (SDFM)

The SDFM is a four-channel digital filter designed specifically for current measurement and resolver position decoding in motor control applications. Each channel can receive an independent delta-sigma modulator bit stream which is processed by four individually programmable digital decimation filters. The filters include a fast comparator for immediate digital threshold comparisons for over-current and under-current monitoring. Also, a filter-bypass mode is available to enable data logging, analysis, and customized filtering. The SDFM pins are configured using the GPIO multiplexer. A key benefit of the SDFM is it enables a simple, costeffective, and safe high-voltage isolation boundary.

SDFM Block Diagram

Reference

[1] TMS320F2837xD Microcontroller Workshop

Comparator Subsystem (CMPSS)

The F2837xD includes eight independent Comparator Subsystem (CMPSS) modules that are useful for supporting applications such as peak current mode control, switched-mode power, power factor correction, and voltage trip monitoring. The Comparator Subsystem modules have the ability to synchronize with a PWMSYNC event.

Comparator Subsystem Block Diagram

Each CMPSS module is designed around a pair of analog comparators which generates a digital output indicating if the voltage on the positive input is greater than the voltage on the negative input. The positive input to the comparator is always driven from an external pin. The negative input can be driven by either an external pin or an internal programmable 12-bit digital-to-analog (DAC) as a reference voltage. Values written to the DAC can take effect immediately or be synchronized with ePWM events. A falling-ramp generator is optionally available to the control the internal DAC reference value for one comparator in the module. Each comparator output is feed through a programmable digital filter that can remove spurious trip signals. The output of the CMPSS generates trip signals to the ePWM event trigger submodule and GPIO structure.

Reference

[1] TMS320F2837xD Microcontroller Workshop

The scheduling algorithm is the software routine that decides which ready state task to transition into the running state.

Round Robin: this scheduler will ensure tasks that share priority are selected to enter the running state in turn. The Round Robin scheduling algorithm in FreeRTOS does not guarantee time is shared equally between tasks of equal priority, only that ready state tasks of equal priority will enter the running state in turn.

Fixed priority: this scheduler does not change the priority assigned to the tasks being scheduled but also does not prevent the tasked from changing their own priority or that of other tasks.

Pre-emptive: this scheduler will immediately preempt the running state task if a task that has priority higher than the running state task enters the ready state. Being pre-empted means being involuntarily moved out of the running state and into the ready state to allow a different task to enter the running state.

Time slicing: this scheduler shares processing time between tasks of equal priority, even when the task does not explicitly yield or enter the blocked state. Scheduling algorithms described as using time slicing will select a new task to enter the running state at the end of each time slice if there are other ready state tasks that have the same priority as running task.

// FreeRTOSConfig.h

// Preemptive priority scheduler
// No automatic round-robin for equal priorities
// Deterministic execution until voluntary block/yield
#define configUSE_PREEMPTION                      1 
#define configUSE_TIME_SLICING                    0

// Priority-based preemptive scheduling
// Round-robin between equal priorities
#define configUSE_PREEMPTION                      1 
#define configUSE_TIME_SLICING                    1 

// FreeRTOSConfig.h

// Preemptive priority scheduler
// No automatic round-robin for equal priorities
// Deterministic execution until voluntary block/yield
#define configUSE_PREEMPTION                      1 
#define configUSE_TIME_SLICING                    0

// Priority-based preemptive scheduling
// Round-robin between equal priorities
#define configUSE_PREEMPTION                      1 
#define configUSE_TIME_SLICING                    1 

// FreeRTOSConfig.h

#define configENABLE_FPU                          1
#define configENABLE_MPU                          0
#define configSUPPORT_STATIC_ALLOCATION           1
#define configSUPPORT_DYNAMIC_ALLOCATION          1
#define configUSE_PREEMPTION                      1
#define configUSE_TIME_SLICING                    1
#define configUSE_IDLE_HOOK                       0
#define configUSE_TICK_HOOK                       0
#define configUSE_QUEUE_SETS                      1
#define configUSE_TRACE_FACILITY                  1
#define configUSE_16_BIT_TICKS                    0
#define configUSE_MUTEXES                         1
#define configUSE_TASK_NOTIFICATIONS              1
#define configUSE_RECURSIVE_MUTEXES               1
#define configUSE_COUNTING_SEMAPHORES             1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION   0
#define configCPU_CLOCK_HZ                        ( SystemCoreClock ) // system_stm32f4xx.c
#define configTICK_RATE_HZ                        ((TickType_t)1000)
#define configMAX_PRIORITIES                      ( 56 )
#define configMINIMAL_STACK_SIZE                  ((uint16_t)128)
#define configTOTAL_HEAP_SIZE                     ((size_t)24*1024)
#define configMAX_TASK_NAME_LEN                   ( 16 )
#define configQUEUE_REGISTRY_SIZE                 8

// FreeRTOSConfig.h

#define configENABLE_FPU                          1
#define configENABLE_MPU                          0
#define configSUPPORT_STATIC_ALLOCATION           1
#define configSUPPORT_DYNAMIC_ALLOCATION          1
#define configUSE_PREEMPTION                      1
#define configUSE_TIME_SLICING                    1
#define configUSE_IDLE_HOOK                       0
#define configUSE_TICK_HOOK                       0
#define configUSE_QUEUE_SETS                      1
#define configUSE_TRACE_FACILITY                  1
#define configUSE_16_BIT_TICKS                    0
#define configUSE_MUTEXES                         1
#define configUSE_TASK_NOTIFICATIONS              1
#define configUSE_RECURSIVE_MUTEXES               1
#define configUSE_COUNTING_SEMAPHORES             1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION   0
#define configCPU_CLOCK_HZ                        ( SystemCoreClock ) // system_stm32f4xx.c
#define configTICK_RATE_HZ                        ((TickType_t)1000)
#define configMAX_PRIORITIES                      ( 56 )
#define configMINIMAL_STACK_SIZE                  ((uint16_t)128)
#define configTOTAL_HEAP_SIZE                     ((size_t)24*1024)
#define configMAX_TASK_NAME_LEN                   ( 16 )
#define configQUEUE_REGISTRY_SIZE                 8

Digital-to-Analog Converter (DAC)

The F2837xD includes three buffered 12-bit DAC modules that can provide a programmable reference output voltage capable of driving an external load. Values written to the DAC can take effect immediately or be synchronized with ePWM events.

Buffered DAC Block Diagram

Two sets of DACVAL registers are present in the buffered DAC module: DACVALA and DACVALS. DACVALA is a read-only register that actively controls the DAC value. DACVALS is a writable shadow register that loads into DACVALA either immediately or synchronized with the next PWMSYNC event. The ideal output of the internal DAC can be calculated as shown in the equation below.

Reference

[1] TMS320F2837xD Microcontroller Workshop

TMS320F28x7x Interrupt Sources

The internal interrupt sources include the general purpose timers 0, 1, and 2, and all of the peripherals on the device. External interrupt sources include the three external interrupt lines, the trip zones, and the external reset pin. The core has 14 interrupt lines. The Peripheral Interrupt Expansion block, known as the PIE block, is connected to the core interrupt lines 1 through 12 and is used to expand the core interrupt capability, allowing up to 192 possible interrupt sources.

TMS320F28x7x Interrupt Processing

By using a series of flag and enable registers, the CPU can be configured to service one interrupt while others remain pending, or perhaps disabled when servicing certain critical tasks. When an interrupt signal occurs on a core line, the interrupt flag register (IFR) for that core line is set. If the appropriate interrupt enable register (IER) is enabled for that core line, and the interrupt global mask (INTM) is enabled, the interrupt signal will propagate to the core.

Once the interrupt service routine (ISR) starts processing the interrupt, the INTM bit is disabled to prevent nested interrupts. The IFR is then cleared and ready for the next interrupt signal. When the interrupt servicing is completed, the INTM bit is automatically enabled, allowing the next interrupt to be serviced. Notice that when the INTM bit is 0, the switch is closed and enabled. When the bit is 1, the switch is open and disabled. The IER is managed by ORing and ANDing mask values. The INTM bit in the status register is managed by using in-line assembly instructions.

TMS320F28x7x IFR, IER, INTM

// Disable CPU interrupts
DINT;

// Disable CPU interrupts and clear all CPU interrupt flags
IER = 0x0000;
IFR = 0x0000;

// Enable global Interrupts and higher priority real-time debug events
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global real-time interrupt DBGM

// Disable CPU interrupts
DINT;

// Disable CPU interrupts and clear all CPU interrupt flags
IER = 0x0000;
IFR = 0x0000;

// Enable global Interrupts and higher priority real-time debug events
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global real-time interrupt DBGM

TMS320F28x7x Peripheral Interrupt Expansion (PIE)

The C28x CPU core has a total of fourteen interrupt lines, of which two interrupt lines are directly connected to CPU Timers 1 and 2 (on INT13 and INT14, respectively) and the remaining twelve interrupt lines (INT1 through INT12) are used to service the peripheral interrupts. A Peripheral Interrupt Expansion (PIE) module multiplexes up to sixteen peripheral interrupts into each of the twelve CPU interrupt lines, further expanding support for up to 192 peripheral interrupt signals. The PIE module also expands the interrupt vector table, allowing each unique interrupt signal to have its own interrupt service routine (ISR), permitting the CPU to support a large number of peripherals.

The PIE module has an individual flag and enable bit for each peripheral interrupt signal. Each of the sixteen peripheral interrupt signals that are multiplexed into a single CPU interrupt line is referred to as a group, so the PIE module consists of 12 groups. Each PIE group has a 16-bit flag register (PIEIFRx), a 16-bit enable register (PIEIERx), and a bit field in the PIE acknowledge register (PIEACK) which acts as a common interrupt mask for the entire group.

For a peripheral interrupt to propagate to the CPU, the appropriate PIEIFR must be set, the PIEIER enabled, the CPU IFR set, the IER enabled, and the INTM enabled. Note that some peripherals can have multiple events trigger the same interrupt signal, and the cause of the interrupt can be determined by reading the peripheral’s status register.

We have already discussed the interrupt process in the core. Now we need to look at the peripheral interrupt expansion block. This block is connected to the core interrupt lines 1 through 12. The PIE block consists of 12 groups. Within each group, there are sixteen interrupt sources. Each group has a PIE interrupt enable register and a PIE interrupt flag register. Note that interrupt lines 13, 14, and NMI bypass the PIE block.

The PIE assignment table maps each peripheral interrupt to the unique vector location for that interrupt service routine. Notice the interrupt numbers on the left represent the twelve core group interrupt lines and the interrupt numbers across the top represent the lower eight of the sixteen peripheral interrupts within the core group interrupt line. The next figure shows the upper eight of the sixteen peripheral interrupts within the core group interrupt line.

Similar to the core interrupt process, the PIE module has an individual flag and enable bit for each peripheral interrupt signal. Each PIE group has a 16-bit flag register, a 16-bit enable register, and a bit field in the PIE acknowledge register which acts as a common interrupt mask for the entire group. The enable PIE bit in the PIECTRL register is used to activate the PIE module.

// Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell 
// Interrupt Service Routines (ISR).
// This will populate the entire table, even if the interrupt 
// is not used in this example.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
InitPieVectTable();

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this project
EALLOW;  
PieVectTable.SCIA_RX_INT = &RXAINT_recv_ready;
PieVectTable.SCIA_TX_INT = &TXAINT_data_sent;
EDIS;    

// Enable group 9 for SCIA RX/TX
IER |= (M_INT9); 

// Enable SCI-A RX interrupt in the PIE: group 9 channel 1
PieCtrlRegs.PIEIER9.bit.INTx1 = 1; 

// Enable SCI-A TX interrupt in the PIE: group 9 channel 2
PieCtrlRegs.PIEIER9.bit.INTx2 = 1; 

// Enable global Interrupts and higher priority real-time debug events
EINT;  // Enable Global interrupt INTM
ERTM;  // Enable Global realtime interrupt DBGM

// Called in RX/TX ISR function
// Acknowledge this interrupt to receive more interrupts from group 9
PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

// Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell 
// Interrupt Service Routines (ISR).
// This will populate the entire table, even if the interrupt 
// is not used in this example.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
InitPieVectTable();

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this project
EALLOW;  
PieVectTable.SCIA_RX_INT = &RXAINT_recv_ready;
PieVectTable.SCIA_TX_INT = &TXAINT_data_sent;
EDIS;    

// Enable group 9 for SCIA RX/TX
IER |= (M_INT9); 

// Enable SCI-A RX interrupt in the PIE: group 9 channel 1
PieCtrlRegs.PIEIER9.bit.INTx1 = 1; 

// Enable SCI-A TX interrupt in the PIE: group 9 channel 2
PieCtrlRegs.PIEIER9.bit.INTx2 = 1; 

// Enable global Interrupts and higher priority real-time debug events
EINT;  // Enable Global interrupt INTM
ERTM;  // Enable Global realtime interrupt DBGM

// Called in RX/TX ISR function
// Acknowledge this interrupt to receive more interrupts from group 9
PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;

TMS320F28x7x PIE Block Initialization

The interrupt vector table, as mapped in the PIE interrupt assignment table, is located in the PieVect.c file. During processor initialization a function call to PieCtrl.c file is used to copy the interrupt vector table to the PIE RAM and then the PIE module is enabled by setting ENPIE to 1. When the CPU receives an interrupt, the vector address of the ISR is fetched from the PIE RAM, and the interrupt with the highest priority that is both flagged and enabled is executed. Priority is determined by the location within the interrupt vector table. The lowest numbered interrupt has the highest priority when multiple interrupts are pending.

In summary, the PIE initialization code flow is as follows. After the device is reset and execution of the boot code is completed, the selected boot option determines the code entry point. In this figure, two different entry points are shown. The one on the left is for memory block M0 RAM, and the one on the right is for flash.

In either case, the CodeStartBranch.asm file has a Long Branch instruction to the entry point of the runtime support library. After the runtime support library completes execution, main is called. In main, a function is called to initialize the interrupt process and enable the PIE module. When the CPU receives an interrupt, the vector address of the ISR is fetched from the PIE RAM, and the interrupt with the highest priority that is both flagged and enabled is executed. Priority is determined by the location within the interrupt vector table.

TMS320F28x7x Interrupt Signal Flow

In summary, the following steps occur during an interrupt process. First, a peripheral interrupt is generated and the PIE interrupt flag register is set. If the PIE interrupt enable register is enabled, then the core interrupt flag register will be set. Next, if the core interrupt enable register and global interrupt mask is enabled, the PIE vector table will redirect the code to the interrupt service routine.

TMS320F28x7D Dual-Core Interrupt Structure

Each C28x CPU core in the F2837xD device has its own PIE module, and each PIE module is configured independently. Some interrupt signals are sourced from shared peripherals that canbe owned by either CPU, and these interrupt signals are sent to both CPU PIE modules regardless of which CPU owns the peripheral. Therefore, if enabled a peripheral owned by one CPU can cause an interrupt on the other CPU.

TMS320F28x7x Interrupt Response and Latency

Reference

[1] TMS320F2837xD Microcontroller Workshop

xTaskCreate()

xTaskCreate() creates a new FreeRTOS task using dynamically allocated memory. It specifies the task function, task name, stack size, input parameter, priority, and an optional task handle for controlling the task later. The function returns pdPASS when the task is created successfully or an error value when memory allocation fails.

#define configSUPPORT_DYNAMIC_ALLOCATION    1

BaseType_t xTaskCreate( 
  TaskFunction_t          pxTaskCode,     // Task function to execute
  const char * const      pcName,         // Task name
  const uint16_t          usStackDepth,   // Task stack size
  void * const            pvParameters,   // Parameter passed to the task
  UBaseType_t             uxPriority,     // Task priority
  TaskHandle_t * const    pxCreatedTask   // Stores the created task handle
)

// ---------------------- Example ----------------------

#define TASK1_TASK_PRIO        2      
#define TASK1_STK_SIZE         256    
TaskHandle_t Task1Task_Handler;       

void vTask1Task(void * pvParameters) {
  while(1) {
	  vTaskDelay(pdMS_TO_TICKS(1000));
	}
}

#define TASK2_TASK_PRIO        3      
#define TASK2_STK_SIZE         256    
TaskHandle_t Task2Task_Handler;       

void vTask2Task(void * pvParameters) {
	while(1) {
		vTaskDelay(pdMS_TO_TICKS(500));
	}
}

xReturn = xTaskCreate((TaskFunction_t ) vTask1Task,
                      (const char *   ) "Task1 Task",
                      (uint16_t       ) TASK1_STK_SIZE,
                      (void *         ) NULL,
                      (UBaseType_t    ) TASK1_TASK_PRIO,
                      (TaskHandle_t * ) &Task1Task_Handler);
                      
if (pdPASS == xReturn) {
	printf("Create vTask1Task successfully.\r\n");
}

xReturn = xTaskCreate((TaskFunction_t ) vTask2Task,
			    		        (const char *   ) "Task2 Task",
						          (uint16_t       ) TASK2_STK_SIZE,
						          (void *         ) NULL,
						          (UBaseType_t    ) TASK2_TASK_PRIO,
						          (TaskHandle_t * ) &Task2Task_Handler);

if (pdPASS == xReturn) {
  printf("Create vTask2Task successfully.\r\n");
}

#define configSUPPORT_DYNAMIC_ALLOCATION    1

BaseType_t xTaskCreate( 
  TaskFunction_t          pxTaskCode,     // Task function to execute
  const char * const      pcName,         // Task name
  const uint16_t          usStackDepth,   // Task stack size
  void * const            pvParameters,   // Parameter passed to the task
  UBaseType_t             uxPriority,     // Task priority
  TaskHandle_t * const    pxCreatedTask   // Stores the created task handle
)

// ---------------------- Example ----------------------

#define TASK1_TASK_PRIO        2      
#define TASK1_STK_SIZE         256    
TaskHandle_t Task1Task_Handler;       

void vTask1Task(void * pvParameters) {
  while(1) {
	  vTaskDelay(pdMS_TO_TICKS(1000));
	}
}

#define TASK2_TASK_PRIO        3      
#define TASK2_STK_SIZE         256    
TaskHandle_t Task2Task_Handler;       

void vTask2Task(void * pvParameters) {
	while(1) {
		vTaskDelay(pdMS_TO_TICKS(500));
	}
}

xReturn = xTaskCreate((TaskFunction_t ) vTask1Task,
                      (const char *   ) "Task1 Task",
                      (uint16_t       ) TASK1_STK_SIZE,
                      (void *         ) NULL,
                      (UBaseType_t    ) TASK1_TASK_PRIO,
                      (TaskHandle_t * ) &Task1Task_Handler);
                      
if (pdPASS == xReturn) {
	printf("Create vTask1Task successfully.\r\n");
}

xReturn = xTaskCreate((TaskFunction_t ) vTask2Task,
			    		        (const char *   ) "Task2 Task",
						          (uint16_t       ) TASK2_STK_SIZE,
						          (void *         ) NULL,
						          (UBaseType_t    ) TASK2_TASK_PRIO,
						          (TaskHandle_t * ) &Task2Task_Handler);

if (pdPASS == xReturn) {
  printf("Create vTask2Task successfully.\r\n");
}

xTaskCreateStatic()

xTaskCreateStatic() creates a new FreeRTOS task using memory supplied by the application instead of the FreeRTOS heap. The caller provides the task stack buffer and task control block, making memory usage fixed and deterministic. The function returns the created task handle when successful or NULL if task creation fails.

 #define configSUPPORT_STATIC_ALLOCATION    1

TaskHandle_t xTaskCreateStatic( 
  TaskFunction_t         pxTaskCode,      // Task function to execute
  const char * const     pcName,          // Task name
  const uint32_t         ulStackDepth,    // Task stack depth
  void * const           pvParameters,    // Parameter passed to the task
  UBaseType_t            uxPriority,      // Task priority
  StackType_t * const    puxStackBuffer,  // User-provided stack buffer
  StaticTask_t * const   pxTaskBuffer     // User-provided task control block
)

// ---------------------- Example ----------------------

#define TASK1_TASK_PRIO        2               
#define TASK1_STK_SIZE         256             
StackType_t Task1TaskStack[TASK1_STK_SIZE];    
StaticTask_t Task1TaskTCB;                     
TaskHandle_t Task1Task_Handler;                

void vTask1Task(void * pvParameters) {
	while(1) {
		vTaskDelay(pdMS_TO_TICKS(1000));
	}
}              

#define TASK2_TASK_PRIO        3               
#define TASK2_STK_SIZE         256             
StackType_t Task2TaskStack[TASK2_STK_SIZE];    
StaticTask_t Task2TaskTCB;                     
TaskHandle_t Task2Task_Handler;   
             
void vTask2Task(void * pvParameters) {
	while(1) {
		vTaskDelay(pdMS_TO_TICKS(500));
	}
}        

static StackType_t IdleTaskStack[configMINIMAL_STACK_SIZE];
static StaticTask_t IdleTaskTCB;

void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
									                  StackType_t **ppxIdleTaskStackBuffer,
									                  uint32_t *pulIdleTaskStackSize ) {
	*ppxIdleTaskTCBBuffer=&IdleTaskTCB;
	*ppxIdleTaskStackBuffer=IdleTaskStack;
	*pulIdleTaskStackSize=configMINIMAL_STACK_SIZE;
}

static StackType_t TimerTaskStack[configTIMER_TASK_STACK_DEPTH];
static StaticTask_t TimerTaskTCB;

void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
									                   StackType_t **ppxTimerTaskStackBuffer,
									                   uint32_t *pulTimerTaskStackSize ) {
	*ppxTimerTaskTCBBuffer=&TimerTaskTCB;
	*ppxTimerTaskStackBuffer=TimerTaskStack;
	*pulTimerTaskStackSize=configMINIMAL_STACK_SIZE;
}

 #define configSUPPORT_STATIC_ALLOCATION    1

TaskHandle_t xTaskCreateStatic( 
  TaskFunction_t         pxTaskCode,      // Task function to execute
  const char * const     pcName,          // Task name
  const uint32_t         ulStackDepth,    // Task stack depth
  void * const           pvParameters,    // Parameter passed to the task
  UBaseType_t            uxPriority,      // Task priority
  StackType_t * const    puxStackBuffer,  // User-provided stack buffer
  StaticTask_t * const   pxTaskBuffer     // User-provided task control block
)

// ---------------------- Example ----------------------

#define TASK1_TASK_PRIO        2               
#define TASK1_STK_SIZE         256             
StackType_t Task1TaskStack[TASK1_STK_SIZE];    
StaticTask_t Task1TaskTCB;                     
TaskHandle_t Task1Task_Handler;                

void vTask1Task(void * pvParameters) {
	while(1) {
		vTaskDelay(pdMS_TO_TICKS(1000));
	}
}              

#define TASK2_TASK_PRIO        3               
#define TASK2_STK_SIZE         256             
StackType_t Task2TaskStack[TASK2_STK_SIZE];    
StaticTask_t Task2TaskTCB;                     
TaskHandle_t Task2Task_Handler;   
             
void vTask2Task(void * pvParameters) {
	while(1) {
		vTaskDelay(pdMS_TO_TICKS(500));
	}
}        

static StackType_t IdleTaskStack[configMINIMAL_STACK_SIZE];
static StaticTask_t IdleTaskTCB;

void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
									                  StackType_t **ppxIdleTaskStackBuffer,
									                  uint32_t *pulIdleTaskStackSize ) {
	*ppxIdleTaskTCBBuffer=&IdleTaskTCB;
	*ppxIdleTaskStackBuffer=IdleTaskStack;
	*pulIdleTaskStackSize=configMINIMAL_STACK_SIZE;
}

static StackType_t TimerTaskStack[configTIMER_TASK_STACK_DEPTH];
static StaticTask_t TimerTaskTCB;

void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
									                   StackType_t **ppxTimerTaskStackBuffer,
									                   uint32_t *pulTimerTaskStackSize ) {
	*ppxTimerTaskTCBBuffer=&TimerTaskTCB;
	*ppxTimerTaskStackBuffer=TimerTaskStack;
	*pulTimerTaskStackSize=configMINIMAL_STACK_SIZE;
}

vTaskDelete()

vTaskDelete() permanently removes a specified FreeRTOS task from the scheduler. Passing a task handle deletes that task, while passing NULL deletes the currently running task.

#define INCLUDE_vTaskDelete    1
void vTaskDelete(TaskHandle_t xTaskToDelete)

// Delete the currently running task
vTaskDelete(NULL);
vTaskDelete(xTaskGetCurrentTaskHandle());

// ---------------------- Example ----------------------

TaskHandle_t Task2Handle = NULL;

void Task1(void *argument) {
  if (Task2Handle != NULL) {
    vTaskDelete(Task2Handle);
    Task2Handle = NULL;
  }
  while(1) {
    printf("Task1 running\n");
    vTaskDelay(pdMS_TO_TICKS(1000));
  }
}

void Task2(void *argument) {
  while(1) {
    printf("Task2 running\n");
    vTaskDelay(pdMS_TO_TICKS(500));
  }
}

#define INCLUDE_vTaskDelete    1
void vTaskDelete(TaskHandle_t xTaskToDelete)

// Delete the currently running task
vTaskDelete(NULL);
vTaskDelete(xTaskGetCurrentTaskHandle());

// ---------------------- Example ----------------------

TaskHandle_t Task2Handle = NULL;

void Task1(void *argument) {
  if (Task2Handle != NULL) {
    vTaskDelete(Task2Handle);
    Task2Handle = NULL;
  }
  while(1) {
    printf("Task1 running\n");
    vTaskDelay(pdMS_TO_TICKS(1000));
  }
}

void Task2(void *argument) {
  while(1) {
    printf("Task2 running\n");
    vTaskDelay(pdMS_TO_TICKS(500));
  }
}

vTaskPrioritySet()

vTaskPrioritySet() changes the priority of an existing FreeRTOS task. The xTask argument specifies the handle of the task whose priority will be changed; passing NULL changes the priority of the currently running task. The uxNewPriority argument specifies the new priority level, which must be between 0 and configMAX_PRIORITIES – 1, where a larger value represents a higher priority. Changing a task’s priority may cause an immediate context switch if another task becomes the highest-priority task that is ready to run.

#define INCLUDE_vTaskPrioritySet    1

void vTaskPrioritySet(
    TaskHandle_t xTask, 
    UBaseType_t uxNewPriority
)

// Set current task priority to 1
vTaskPrioritySet(NULL, 1);

// ---------------------- Example ----------------------

TaskHandle_t red_handle, green_handle;

xTaskCreate(vRedLedControllerTask,
			      "Red Led Controller",
			      100,
			      NULL,
			      1, // task priority
			      &red_handle);

xTaskCreate(vGreenLedControllerTask,
			      "Green Led Controller",
			      100,
			      NULL,
			      1, // task priority
			      &green_handle);

// Red Led Controller Task
void vRedLedControllerTask(void *pvParamters) {
	while(1){
		HAL_GPIO_TogglePin(GPIOD, RED);
		RedTaskProfiler++;
		vTaskDelay(pdMS_TO_TICKS(1000));
		// Set green task with priority of 3
		vTaskPrioritySet(green_handle, 3);
	}
}

// Green Led Controller Task
void vGreenLedControllerTask(void *pvParamters) {
	while(1){
		HAL_GPIO_TogglePin(GPIOD, GREEN);
		GreenTaskProfiler++;
		vTaskDelay(pdMS_TO_TICKS(500));
	}
}

#define INCLUDE_vTaskPrioritySet    1

void vTaskPrioritySet(
    TaskHandle_t xTask, 
    UBaseType_t uxNewPriority
)

// Set current task priority to 1
vTaskPrioritySet(NULL, 1);

// ---------------------- Example ----------------------

TaskHandle_t red_handle, green_handle;

xTaskCreate(vRedLedControllerTask,
			      "Red Led Controller",
			      100,
			      NULL,
			      1, // task priority
			      &red_handle);

xTaskCreate(vGreenLedControllerTask,
			      "Green Led Controller",
			      100,
			      NULL,
			      1, // task priority
			      &green_handle);

// Red Led Controller Task
void vRedLedControllerTask(void *pvParamters) {
	while(1){
		HAL_GPIO_TogglePin(GPIOD, RED);
		RedTaskProfiler++;
		vTaskDelay(pdMS_TO_TICKS(1000));
		// Set green task with priority of 3
		vTaskPrioritySet(green_handle, 3);
	}
}

// Green Led Controller Task
void vGreenLedControllerTask(void *pvParamters) {
	while(1){
		HAL_GPIO_TogglePin(GPIOD, GREEN);
		GreenTaskProfiler++;
		vTaskDelay(pdMS_TO_TICKS(500));
	}
}

uxTaskPriorityGet()

uxTaskPriorityGet() returns the current priority of a FreeRTOS task. The xTask argument is the handle of the task whose priority is requested; passing NULL returns the priority of the currently running task. The function returns the task’s priority as a value of type UBaseType_t, where a larger value represents a higher priority.

#define INCLUDE_uxTaskPriorityGet    1
UBaseType_t uxTaskPriorityGet(const TaskHandle_t xTask)

// ---------------------- Example ----------------------

TaskHandle_t green_handle;
uint32_t green_priority;

// Get priority green LED task
green_priority = uxTaskPriorityGet(green_handle);

#define INCLUDE_uxTaskPriorityGet    1
UBaseType_t uxTaskPriorityGet(const TaskHandle_t xTask)

// ---------------------- Example ----------------------

TaskHandle_t green_handle;
uint32_t green_priority;

// Get priority green LED task
green_priority = uxTaskPriorityGet(green_handle);

vTaskSuspend()

vTaskSuspend() suspends a FreeRTOS task, preventing it from being scheduled until it is resumed using vTaskResume() or xTaskResumeFromISR(). The xTaskToSuspend argument specifies the handle of the task to suspend; passing NULL suspends the currently running task. A suspended task does not consume CPU time and remains suspended indefinitely until explicitly resumed.

#define INCLUDE_vTaskSuspend    1
void vTaskSuspend(TaskHandle_t xTaskToSuspend)

// ---------------------- Example ----------------------

vTaskSuspend(NULL);
vTaskSuspend(blue_handle);

void vBlueLedControllerTask(void *pvParamters) {
	while(1) {
		HAL_GPIO_TogglePin(GPIOD, BLUE);
		BlueTaskProfiler++;
    vTaskDelay(pdMS_TO_TICKS(500));
		vTaskSuspend(NULL); // Suspend task itself
	}
}

#define INCLUDE_vTaskSuspend    1
void vTaskSuspend(TaskHandle_t xTaskToSuspend)

// ---------------------- Example ----------------------

vTaskSuspend(NULL);
vTaskSuspend(blue_handle);

void vBlueLedControllerTask(void *pvParamters) {
	while(1) {
		HAL_GPIO_TogglePin(GPIOD, BLUE);
		BlueTaskProfiler++;
    vTaskDelay(pdMS_TO_TICKS(500));
		vTaskSuspend(NULL); // Suspend task itself
	}
}

vTaskResume()

vTaskResume() resumes a task that was previously suspended using vTaskSuspend(), allowing it to return to the Ready state and be scheduled again. The xTaskToResume argument is the handle of the suspended task to resume. If the resumed task has a higher priority than the currently running task, a context switch may occur immediately.

void vTaskResume(TaskHandle_t xTaskToResume)

// ---------------------- Example ----------------------

TaskHandle_t xTaskHandle;
vTaskResume(xTaskHandle);

void vTaskResume(TaskHandle_t xTaskToResume)

// ---------------------- Example ----------------------

TaskHandle_t xTaskHandle;
vTaskResume(xTaskHandle);

xTaskResumeFromISR()

xTaskResumeFromISR() resumes a task that was previously suspended by vTaskSuspend() and is specifically designed to be called from an interrupt service routine. The xTaskToResume argument is the handle of the task to resume. The function returns pdTRUE when resuming the task causes a higher-priority task to become ready, indicating that a context switch should be requested before leaving the ISR; otherwise, it returns pdFALSE.

BaseType_t xTaskResumeFromISR(TaskHandle_t xTaskToResume)

// ---------------------- Example ----------------------

void EXTI0_IRQHandler(void) {
    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
}

void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
	BaseType_t YieldRequired = pdFALSE;
  if (GPIO_Pin == GPIO_PIN_0) {
    YieldRequired = xTaskResumeFromISR(Task1Task_Handler);
    if(YieldRequired == pdTRUE) {
      portYIELD_FROM_ISR(YieldRequired);
    }
  }
}

BaseType_t xTaskResumeFromISR(TaskHandle_t xTaskToResume)

// ---------------------- Example ----------------------

void EXTI0_IRQHandler(void) {
    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
}

void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
	BaseType_t YieldRequired = pdFALSE;
  if (GPIO_Pin == GPIO_PIN_0) {
    YieldRequired = xTaskResumeFromISR(Task1Task_Handler);
    if(YieldRequired == pdTRUE) {
      portYIELD_FROM_ISR(YieldRequired);
    }
  }
}

vTaskDelayUntil()

vTaskDelayUntil() blocks a task until a specified absolute wake time, making it useful for creating tasks that execute at a fixed and consistent period. The pxPreviousWakeTime argument points to a variable containing the task’s previous wake time; it is automatically updated after each call. The xTimeIncrement argument specifies the period between executions in system ticks. Unlike vTaskDelay(), this function compensates for task execution time and helps prevent timing drift.

#define INCLUDE_vTaskDelayUntil    1

void vTaskDelayUntil(
  TickType_t * const pxPreviousWakeTime, 
  const TickType_t xTimeIncrement
)

// ---------------------- Example ----------------------

const TickType_t xPeriod = pdMS_TO_TICKS(500);

// Blue Led Controller Task
void vBlueLedControllerTask(void *pvParamters) {
	TickType_t xLastWakeTime = xTaskGetTickCount();
	while(1) {
		// xLastWakeTime value will be updated automatically
		vTaskDelayUntil(&xLastWakeTime, xPeriod);
		HAL_GPIO_TogglePin(GPIOD, BLUE);
		BlueTaskProfiler++;
	}
}

#define INCLUDE_vTaskDelayUntil    1

void vTaskDelayUntil(
  TickType_t * const pxPreviousWakeTime, 
  const TickType_t xTimeIncrement
)

// ---------------------- Example ----------------------

const TickType_t xPeriod = pdMS_TO_TICKS(500);

// Blue Led Controller Task
void vBlueLedControllerTask(void *pvParamters) {
	TickType_t xLastWakeTime = xTaskGetTickCount();
	while(1) {
		// xLastWakeTime value will be updated automatically
		vTaskDelayUntil(&xLastWakeTime, xPeriod);
		HAL_GPIO_TogglePin(GPIOD, BLUE);
		BlueTaskProfiler++;
	}
}