TI C2000: Hardware Acceleration Subsystem – Direct Memory Access (DMA)

The DMA module provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, effectively freeing up the CPU for other functions. Each CPU subsystem has its own DMA and using the DMA is ideal when an application requires a significant amount of time spent moving large amounts of data from off-chip memory to on-chip memory, or from a peripheral such as the ADC result register to a memory RAM block, or between two peripherals. Additionally, the DMA is capable of rearranging the data for optimal CPU processing such as binning and ping-pong buffering.

Specifically, the DMA can read data from the ADC result registers, transfer to or from memory blocks G0 through G15, IPC RAM, EMIF, transfer to or from the McBSP and SPI, and also modify registers in the ePWM. A DMA transfer is started by a peripheral or software trigger. There are six independent DMA channels, where each channel can be configured individually and each DMA channel has its own unique PIE interrupt for CPU servicing. All six DMA channels operate the same way, except channel 1 can be configured at a higher priority over the other five channels. At its most basic level the DMA is a state machine consisting of two nested loops and tightly coupled address control logic which gives the DMA the capability to rearrange the blocks of data during the transfer for post processing. When a DMA transfers is completed, the DMA can generate an interrupt.

• Word
  • 16 or 32 bits
  • Word size is configurable per DMA channel
• Burst
  • Consists of multiple words
  • Smallest amount of data transferred at one time
• Burst Size
  • Number of words per burst
  • Specified by BURST_SIZE register
    • 5-bit N-1 value (maximum of 32 words/burst)
• Transfer
  • Consists of multiple bursts
• Transfer Size
  • Number of bursts per transfer
  • Specified by TRANSFER_SIZE register
    • 16-bit N-1 value – exceeds any practical requirements

• 4 cycles/word (5 for McBSP reads)
• 1 cycle delay to start each burst
• 1 cycle delay returning from CH1 high priority interrupt
• 32-bit transfer doubles throughput (except McBSP, which supports 16-bit transfers only)

• DMA has priority over CPU
  • If a multi-cycle CPU access is already in progress, DMA stalls until current CPU access finishes
  • The DMA will interrupt back-to-back CPU accesses
• Can the CPU be locked out?
  • Generally no
  • DMA is multi-cycle transfer; CPU will sneak in an access when the DMA is accessing the other end of the transfer (e.g. while DMA accesses destination location, the CPU can access the source location)

[1] TMS320F2837xD Microcontroller Workshop