TI C2000: External Memory Interface (EMIF)

External Memory Interface (EMIF)

This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories utilizing a 32-bit/16-bit data bus. The purpose of this EMIF is to provide a means for the CPU to connect to a variety of external devices including:

• Single data rate (SDR) SDRAM
• Asynchronous devices including NOR Flash and SRAM

A common use for the EMIF is to interface with both a flash device and an SDRAM device simultaneously.

Interfacing to SDRAM

The EMIF supports a glueless interface to SDRAM devices with the following characteristics:

• Pre-charge bit is A[10]
• The number of column address bits is 8, 9, 10, or 11
• The number of row address bits is 13, 14, 15, or 16
• The number of internal banks is 1, 2, or 4

Interfacing to Asynchronous Memory

The EMIF easily interfaces to a variety of asynchronous devices including NOR Flash and SRAM. It can be operated in two major modes

• Normal Mode
• Select Strobe Mode

EMIF Performance

Reference

[1] TMS320F2837xD Microcontroller Workshop