This Guide Is Still Being Expanded – More to Come
STM32 Microcontroller and FreeRTOS Development- FreeRTOS on TI C2000 C28x vs. STM32 MCUs
- Stack Differences
- FreeRTOS Data Type Mapping for TI C2000 C28x MCU
- Heap and Memory Differences
- Interrupt Model
- Example: FreeRTOS Demo for F28377S Coreboard V1.3
| Setting | TI C2000 C28x (TMS320F2837xx) | STM32F407xx |
|---|---|---|
| CPU architecture | TI C28x, 16-bit address unit | ARM Cortex-M4F, 8-bit byte |
| CPU clock | Up to 200 MHz | Up to 168 MHz |
| Tick rate | 1 kHz | 1 kHz |
| FreeRTOS tick source | CPU Timer 2 | Cortex-M SysTick |
| Property | TI C2000 C28x (TMS320F2837xx) | STM32F407xx |
|---|---|---|
| CHAR_BIT | 16 | 8 |
| sizeof(StackType_t) | 1 C byte = 16 bits | 4 bytes = 32 bits |
| Physical bytes per stack element | 2 | 4 |
| Stack growth | Upward | Downward |
| BaseType_t | 16-bit | 32-bit |
| Stack alignment | 2 C address units = 4 physical bytes | 8 physical bytes |
On TI C2000, FreeRTOS-allocated memory begins on a boundary aligned to two C28x address units, equivalent to four conventional bytes. On STM32, FreeRTOS-allocated memory begins on an 8-byte boundary, meaning its starting address is a multiple of eight.
// TI C2000 C28x, portmacro.h
#define portBYTE_ALIGNMENT 2
// STM32, portmacro.h
#define portBYTE_ALIGNMENT 8| FreeRTOS Type | C28x Underlying Type |
|---|---|
| BaseType_t | int16_t |
| UBaseType_t | uint16_t |
| StackType_t | uint16_t |
| TickType_t | uint32_t |
| portCHAR | uint16_t |
| portSHORT | uint16_t |
| portLONG | uint32_t |
| portBASE_TYPE | uint16_t |
| portSTACK_TYPE | uint16_t |
The C28 project explicitly declares ucHeap[] and places it in .freertosHeap. The STM32 project lets heap_4.c declare the heap internally in .bss.
The C28x stack pointer is more restricted than the Cortex-M stack pointer. C28x task stacks generally must reside in the lower, stack-addressable data-memory range. This is why C28x projects often explicitly place the FreeRTOS heap in a suitable RAM section:
With FPU32 enabled, C28x saves floating-point state on every task context switch, increasing task stack usage. Cortex-M4F typically uses lazy FPU stacking, saving extra floating-point registers only when needed.
On C28x, a request of 100 allocates 100 sixteen-bit addressable units because the smallest addressable unit is 16 bits. This corresponds to 200 conventional eight-bit bytes of physical storage. On STM32, a request of 100 allocates 100 standard eight-bit bytes, since memory is byte-addressable.
C2000 does not use NVIC or BASEPRI. It uses:
- INTM: global maskable-interrupt enable/disable bit
- IER: CPU interrupt enable register
- IFR: CPU interrupt flag register
- PIE: Peripheral Interrupt Expansion controller
- PIE: Peripheral Interrupt Expansion controller CPU interrupt groups INT1 through INT14
// portmacro.h
#define portDISABLE_INTERRUPTS() __asm(" setc INTM")
#define portENABLE_INTERRUPTS() __asm(" clrc INTM")INTM = 1 -> all normal maskable C28x interrupts are disabled
INTM = 0 -> normal maskable interrupts are allowed
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