TI C2000 Real-Time Microcontroller: Control, Sensing, and Communication

TI C2000 Real-time Microcontroller (TMS320F28x7x / F2837xx / F2838x)

	TI
Coding & Debugging	Code Composer Studio
PinMux Setting	SysConfig
Programmer	UniFlash, C2Prog
Real-time Diagnose	RTOS Analyzer, Runtime Object Viewer
Library	Direct, Bit Fields, DriverLib
RTOS	TI-RTOS (SYS/BIOS), FreeRTOS
Debugger	XDS100v2, XDS2xx
Sensing & Control	ePWM, eQEP, eCAP, SDFM, CLA
Peripheral (Communication)	USB, CAN, CAN-FD, LIN, SSI, FSI, SPI, McBSP, SCI/UART, I2C, Ethernet, EtherCAT
Peripheral (Other)	CLB

1. Introduction to TI C2000 Core Board V1.3
- TI Dual-core TMS320F28375D Core Board V1.3
- TMS320F28375D Core Board V1.3 GPIO and Peripheral Muxing
- Comparison between LAUNCHXL-F28379D and Core Board V1.3
2. TI C2000 Architecture Overview
- Device Comparison
- TMS320F2837xD/F2838xD Dual-Core Block Diagram
- Core Block Diagram
- CPU Internal Bus Structure
- CPU Pipeline
- Math Accelerators: Viterbi / Complex Math Unit (VCU-II)
- Math Accelerators: Trigonometric Math Unit (TMU)
3. Memory-Map and Linker Command File
- TMS320F28x7x Memory Map
- TMS320F2837xD Memory Map
- TMS320C28x C/C++ COFF and EABI Data Types
- Linker Command File
- Linker Command File – SECTIONS
- Linker Command File – Example
  - 2837xD_FLASH_Lnk_cpu1.cmd
  - 2837xD_FLASH_Lnk_cpu1_cla1.cmd
  - 2837xD_FLASH_Lnk_cpu1_cla1_ipc.cmd
  - 2837xD_FLASH_Lnk_cpu2_cla1_ipc.cmd
4. Peripheral Register Header Files
- Register Programming Model: Direct Register Access, BitField, DriverLib
- Header File Structure Naming Conventions
- Header Files
- Peripheral Header Files
- Global Variable Definitions File
- Mapping Structures to Memory
5. Reset and Boot Process
- Reset Sources
- Dual-Core Boot Process
- Reset – Bootloader
- Emulation Boot Mode
- Stand-Alone Boot Mode
- Reset Code Flow
- Emulation Boot Mode using GEL
- main()
- Peripheral Software Reset Registers
6. Interrupts
- Interrupt Sources
- Interrupt Processing
- IFR, IER, INTM
- Peripheral Interrupt Expansion (PIE)
- PIE Block Initialization
- Interrupt Signal Flow
- Dual-Core Interrupt Structure
- Interrupt Response and Latency
7. System Initialization
- Oscillator / PLL Clock Module
- Dual-Core System Clock
- Watchdog Timer
- Low Power Modes
- Register Protection
8. General-Purpose I/O (GPIO) and PinMux
- General Purpose Digital I/O
- GPIO Input Qualification
- GPIO Input X-Bar
- GPIO Output X-Bar
- External Interrupts
9. Analog Subsystem – Analog-to-Digital Converter (ADC)
- ADC Subsystem
- ADC Module Block Diagram
- ADC SOCx Functional Diagram
- ADC Triggering
- ADC Ping-Pong Triggering
- ADC Conversion Priority
  - Example – Round Robin Priority
  - Example – High Priority
  - Example – Round Robin Burst Mode with High Priority
- ADC Post Processing Block
- ADC Clocking Flow
- ADC Converter Registers
- ADC Control Registers
- ADC Conversion Result Registers
- ADC Signed Input Voltages
- ADC Calibration and Reference
10. Analog Subsystem – Digital-to-Analog Converter (DAC)
- Digital-to-Analog Converter (DAC)
- Buffered DAC Block Diagram
11. Analog Subsystem – Comparator Subsystem (CMPSS)
- Comparator Subsystem (CMPSS)
- Comparator Subsystem Block Diagram
12. Analog Subsystem – Sigma Delta Filter Module (SDFM)
- Sigma Delta Filter Module (SDFM)
- SDFM Block Diagram
13. Control – enhanced Pulse Width Modulation (ePWM)
14. Control – enhanced Capture (eCAP)
15. Control – enhanced Quadrature Encoder Pulse Module (eQEP)
16. Communication – Serial Communication Interface (SCI)
- Serial Communications Interface (SCI)
- SCI Multiprocessor Wake-Up Modes
- SCI Summary
17. Communication – Serial Peripheral Interface (SPI)
- Serial Peripheral Interface (SPI)
- SPI Transmit / Receive Sequence
- SPI Summary
18. Communication – Inter-Integrated Circuit (I2C)
- Inter-Integrated Circuit (I2C)
- I2C Operating Modes and Data Formats
- I2C Summary
19. Communication – Controller Area Network (CAN)
- Controller Area Network (CAN)
- CAN Bus and Node
- Principles of Operation
- Message Format and Block Diagram
- CAN Summary
20. Communication – Universal Serial Bus (USB)
- Universal Serial Bus (USB) Controller
- USB Communication
- Enumeration
- USB Hardware
- USB Summary
21. Communication – Multichannel Buffered Serial Port (McBSP)
- Multichannel Buffered Serial Port (McBSP)
- McBSP Definition
- Multi-Channel Selection
- McBSP Summary
22. Multi-Core Communication – Inter-Processor Communications (IPC)
- Inter-Processor Communications (IPC)
- IPC Global Shared RAM
- IPC Message RAM
- IPC Message Registers
- IPC Interrupts and Flags
- IPC Data Transfer
- IPC Software Solutions Summary
23. Hardware Acceleration Subsystem – Direct Memory Access (DMA)
- Direct Memory Access (DMA)
- DMA Operation
- DMA Example
- DMA Channel Priority Modes
- DMA Throughput
- DMA Registers
24. Hardware Acceleration Subsystem – Control Law Accelerator (CLA)
- Control Law Accelerator (CLA)
- CLA Memory and Register Access
- CLA Tasks
- CLA Registers
- CLA Initialization
- CLA Task Programming
- CLA C Language Implementation and Restrictions
- CLA Assembly Language Implementation
- CLA Code Debugging
25. External Memory Interface (EMIF)
- External Memory Interface (EMIF)
- Interfacing to SDRAM
- Interfacing to Asynchronous Memory
- EMIF Performance
Configurable Logic Block (CLB)
TI C2000 TMS320F2838x Only
Communication – Modular Controller Area Network (CAN-FD)
Communication – Fast Serial Interface (FSI)
Communication – Ethernet Media Access Controller (EMAC)
Communication – EtherCAT Subordinate Device Controller (ESC)