Work in Progress
FreeRTOS on TI C2000 C28x vs. STM32 MCUs
| Setting | TI C2000 C28x (TMS320F2837xx) | STM32F407xx |
|---|---|---|
| CPU architecture | TI C28x, 16-bit address unit | ARM Cortex-M4F, 8-bit byte |
| CPU clock | Up to 200 MHz | Up to 168 MHz |
| Tick rate | 1 kHz | 1 kHz |
| FreeRTOS tick source | CPU Timer 2 | Cortex-M SysTick |
Stack Differences on TI C2000 C28x vs. STM32 MCUs
| Property | TI C2000 C28x (TMS320F2837xx) | STM32F407xx |
|---|---|---|
| CHAR_BIT | 16 | 8 |
| sizeof(StackType_t) | 1 C byte = 16 bits | 4 bytes = 32 bits |
| Physical bytes per stack element | 2 | 4 |
| Stack growth | Upward | Downward |
| BaseType_t | 16-bit | 32-bit |
| Stack alignment | 2 C address units = 4 physical bytes | 8 physical bytes |
Heap and Memory Differences
The C28 project explicitly declares ucHeap[] and places it in .freertosHeap. The STM32 project lets heap_4.c declare the heap internally in .bss.
Interrupt Model
C2000 does not use NVIC or BASEPRI. It uses:
- INTM: global maskable-interrupt enable/disable bit
- IER: CPU interrupt enable register
- IFR: CPU interrupt flag register
- PIE: Peripheral Interrupt Expansion controller
- PIE: Peripheral Interrupt Expansion controller CPU interrupt groups INT1 through INT14
The C28x port protects the kernel using the global INTM bit:
// portmacro.h
#define portDISABLE_INTERRUPTS() __asm(" setc INTM")
#define portENABLE_INTERRUPTS() __asm(" clrc INTM")
Therefore, during a FreeRTOS critical section:
INTM = 1 -> all normal maskable C28x interrupts are disabled
INTM = 0 -> normal maskable interrupts are allowed
Unlike STM32, C2000 FreeRTOS does not leave a class of high-priority maskable interrupts running. Consequently, it does not need a “maximum syscall interrupt priority” boundary.
Back to top of the page